The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device in which a thin oxide film is formed adjacent to a thick oxide film formed on an impurity diffusion layer, like a flat-cell ROM (Read Only Memory).
FIGS. 3A to 3D show some steps of a method of manufacturing a conventional flat-cell ROM. As shown in FIG. 3A, after an oxide film 12 and a nitride film 13 are sequentially formed on the surface of a p-type semiconductor substrate 11, the nitride film 13 and the oxide film 12 in a region except for an element formation region are removed by RIE (Reactive Ion Etching) or the like using a photoresist mask. Element isolation oxide films 14 are formed by LOCOS (LOCal Oxidation of Silicon) on the surface of the semiconductor substrate 11 in the region except for the element formation region. As shown in FIG. 3B, the photoresist mask, the nitride film 13, and the oxide film 12 in the element formation region are sequentially removed by etching.
As shown in FIG. 3C, after thermal oxidation is performed again to form an oxide film 20 on the surface of the semiconductor substrate 11 in the element formation region surrounded by the element isolation oxide films 14, arsenic is ion-implanted in the surface of the semiconductor substrate 11 by using a photoresist mask 15 having openings at predetermined portions, thereby forming buried n.sup.+ -type layers 16. Then, a p- or n-type well is formed by photolithography and ion implantation. FIG. 3D shows a state wherein a p-type well 18 is formed. The oxide film 20 is removed by etching, and heat treatment is performed to form gate oxide films 19 on the p-type well 18. Since the dose is high in the region of the buried n.sup.+ -type layer 16, oxide films having a high growth rate, i.e., enhanced oxide films 17 are formed at the same time as the gate oxide films 19.
Assume that arsenic ion implantation conditions are 50 to 100 keV and a dose of 5E14 to 5E15 cm.sup.-2, and the gate oxide film 19 having a thickness of about 150 .ANG. is formed by steam oxidation at 850.degree. as a gate oxidation condition. In this case, the enhanced oxide film 17 on the buried n.sup.+ -type layer 16 has a thickness of about 300 .ANG.. Therefore, if the gate oxide film 19 is formed to a thickness of 100 .ANG. or less along with micropatterning of an element, the thickness of the enhanced oxide film 17 is decreased to 200 .ANG. or less.
In this manner, according to the conventional manufacturing method, since the gate oxide film 19 and the enhanced oxide film 17 are simultaneously formed, the thickness of the enhanced oxide film 17 decreases along with a decrease in thickness of the gate oxide film 19. As a result, inconvenience occurs when the buried n.sup.+ -type layer 16 is aligned by using the enhanced oxide film 17 as an alignment mark in the subsequent step. That is, a step on the substrate surface which is formed at the end portion of the enhanced oxide film 17 formed thick is generally used as an alignment mark. However, if the step on the substrate surface is relaxed due to the decrease in thickness of the gate oxide film 19, the alignment accuracy decreases or alignment fails when alignment is performed by detecting the step by laser scanning.
In the conventional manufacturing method, the oxidation time required for forming the gate oxide film 19 to a predetermined thickness is relatively long, and the buried n.sup.+ -type layer 16 is exposed on the substrate surface. At this time, since the ion implantation dose is as relatively high as 5E14 to 5E15 cm.sup.-2, a gate oxidation furnace is contaminated by out-diffusion of an n.sup.+ -type impurity.